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ASIC Design Verification Engineer

發(fā)布時間:2019-1-29 12:01    發(fā)布者:KT咨詢
關(guān)鍵詞: Design , verification
NO.487-【獵頭職位:深圳需要五位 ASIC Design Verification Engineer】聯(lián)系人:Raymond-Chen,郵箱:hr@kthr.com,微信也可查詢職位了!打開手機微信,搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加,歡迎大家關(guān)注!
Job Description:
OURS is seeking an outstanding ASICVerification Engineer to verify the design and implementation. This positionoffers the opportunity to have a real impact in the dynamic andtechnology-focused company. You will be responsible for
Ø  Verifying the design, architecture andmicro-architecture using advanced verification methodologies
Ø  Defining the verification scope andcontributing to the development of the verification infrastructure
Ø  Collaborating with architects, designers, andsoftware engineers across sites to accomplish verification targets
Job Requirement:
Ø  A BS degree in Electrical Engineering,Computer Science or other equivalent disciplines with > 3 years of relevantwork or research experience, or a MS degree of the above areas with > 2years of similar experience.
Ø  Experience in verification using randomstimulus along with functional coverage and assertion-based verificationmethodologies
Ø  Fluency in Object Oriented Programming withC++ and/or SystemVerilog
Ø  Exposure to design and verification tools(VCS or equivalent simulation tools, debug tools like Debussy, GDB), andmethodologies (UVM or equivalent)
Ø  Passionate about debugging and comprehensiveproblem-solving skills
Ø  High proficiency in English - both orally andin writing form.
Ø  Excellent communication skills; botharticulate and a good listener.
Ø  Self-driven, result-oriented; able tomulti-task and determine priorities.
Ø  A proven fast learner and a team player.
Ø  Experience of working with foreign coworkersand remote teams is a plus.
福利:股票期權(quán)  住房補貼  五險一金  帶薪年假

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