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作者：myshitshit 再貼一個(gè)測(cè)試設(shè)計(jì)的職位描述 Job Function: Definition, architecture, modeling, verification, bring-up, debug and support of structural test for achievement of high defect coverage of microprocessor designs from product definition through production. Responsibilities: • Define, model and verify DFT features. • Utilize industry-standard ATPG tools to generate patterns and verify them. • Simulate/verify DFT patterns using Verilog VCS. • Bring-up and debug DFT patterns on the ATE. • Develop, implement and support DFT methodologies. • Proficient with at-speed scan architectures, memory BIST and/or logic BIST. • Proficient with coding/scripting using Perl. • Mentor less senior DFT engineers and lead their efforts in achieving project objectives. • Collaborate with engineering professionals across the company in order to advance the state of the art of DFT and test practices at AMD. Preferred Experience: • Master of EE or above. 4+ years DFT experience. • Experience in microprocessor design or experience in handling complex SOC designs. • Knowledgeable about industrial standards in DFT such as LBIST/JTAG/MBIST. • Knowledgeable about ATE testers and ATPG standard practices. • Expert knowledge of Verilog, RTL, Verilog simulators and waveform debugging tools. • Good debugging capability with both RTL and gate-level simulations. • Good communication skills and the ability to work with geographically distributed design sites. 可以看出要求很多。一些剛進(jìn)入電路行業(yè)的人會(huì)認(rèn)為測(cè)試相關(guān)的事情技術(shù)含量很低啊，當(dāng)然測(cè)試間的操作員是要做很多重復(fù)性勞動(dòng)。但是測(cè)試設(shè)計(jì)完全是另一回事。大些的企業(yè)里，測(cè)試設(shè)計(jì)工程師跟測(cè)試工程師是2個(gè)不同職位。前者主要負(fù)責(zé)制定測(cè)試策略，添加測(cè)試電路，生成測(cè)試向量，協(xié)助后者調(diào)通測(cè)試程序。后者主要在機(jī)臺(tái)上調(diào)通程序，處理量產(chǎn)中測(cè)試相關(guān)問題，分析失效原因，協(xié)助其他工藝提高良品率。小點(diǎn)的公司可能2件事情同一個(gè)人做，或者干脆由管綜合的人做前者的事情，后者由工廠相關(guān)人員協(xié)助完成。由于大部分公司做的產(chǎn)品可靠性要求不高，所以很多時(shí)候只是在芯片上運(yùn)行一下功能測(cè)試的程序，不需要做全面的掃描，對(duì)測(cè)試設(shè)計(jì)的專業(yè)性也就沒那么高。另外很多公司甚至沒有量產(chǎn)經(jīng)歷，導(dǎo)致真正水平較高的測(cè)試設(shè)計(jì)人員很難找到。一般來說做測(cè)試設(shè)計(jì)的人員都是有過一段時(shí)間邏輯電路設(shè)計(jì)經(jīng)驗(yàn)的，測(cè)試工程師大部分是半導(dǎo)體廠直接招的畢業(yè)生練出來的。如果有公司要染指利潤，可靠性要求較高的汽車電子，航空電子，最重要的是要有夠水平的測(cè)試設(shè)計(jì)人員。 數(shù)字電路方面基本就這些崗位，模擬電路的崗位基本也就電路設(shè)計(jì)跟版圖設(shè)計(jì)，一個(gè)電路公司里邊如果有小妞，基本會(huì)出現(xiàn)在畫版圖的位置上，不過這些也基本是屌絲女，白富美基本不會(huì)光顧這種行業(yè)。下面看看這2種崗位的需求。 Position Description Analog IC designer - responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. Background should demonstrate good problem solving skills, excellent analog aptitude, communication skills, and ability to work cooperatively in a team environment. The candidate would become part of analog IC design team creating leading edge IP (ADC's; DAC's; PLL's; SerDes) in leading edge processes (28nm and below). Position Requirements Must be familiar with design concepts for some basic analog functions including some of the following: data conversion, switched-capacitor circuits, op-amps, comparators, voltage and current references, phase-locked loops. Must be proficient in using CAD tools for circuit simulation, verification, and layout. 2-3 years employment or intern epxerience. Postion is also open to high performing recent EE graduate who has completed coursework that includes analog design. 版圖工程師 Key Areas of Responsibility: • Technical tasks involved are full customer layout design， layout check and verification. Required knowledge, skills, abilities: • Understanding the basic process and device knowledge. It is preferred to have knowledge on HV process/device. • Familiar with layout tools, verification tools, command file based on cadence environment. Additional knowledge, skills, abilities, certifications: • Understanding basic IC design knowledge, especially in analog IC. Knowing of ESD and latch-up related will be considered a plus. Required education and experience: • At least Bachelor degree is required. More than one year of prior experience in full-custom –design analog IC layout is necessary. Layout experience in Power management IC with HV process is preferred. 現(xiàn)在畫模擬版圖電路基本都是cds的輸入仿真工具，外加mentor的驗(yàn)證工具，現(xiàn)在模擬電路設(shè)計(jì)基本停留在cad階段，eda還處在概念期，所以對(duì)人員經(jīng)驗(yàn)要求較高。很多公司對(duì)有經(jīng)驗(yàn)的電路工程師的定義是8年以上，可見這個(gè)崗位成才挺慢。做模擬電路需要對(duì)電路理論，半導(dǎo)體制程都有些了解，如果做高頻電路，還要懂電磁波跟信號(hào)處理方面的東西，這些東西上大學(xué)期間不要說學(xué)生能夠完全搞清楚的沒幾個(gè)，即使大部分教這些課程的叫獸僵尸，也只不過能把課本念熟練，真正完全理解的也不多見。所以真正有水平的模擬電路設(shè)計(jì)師，尤其是射頻集成電路設(shè)計(jì)的，即使世界范圍內(nèi)也是稀缺資源。當(dāng)然國內(nèi)現(xiàn)在也有不少在做模擬電路的，但是大部分是做電源管理芯片，這個(gè)大概算模擬電路中的入門產(chǎn)品吧，甚至有些小公司直接翻抄版圖，也能出些產(chǎn)品。整體來說，這個(gè)崗位屬于需求大于供給的，即使水平一般，也不愁沒地方工作，除非鬧經(jīng)濟(jì)危機(jī)所有公司都裁員的時(shí)候。這個(gè)工作如果能把需要學(xué)的都完全搞明白了，其實(shí)勞動(dòng)量也就是算一下電路參數(shù)，做個(gè)仿真，指導(dǎo)一下版圖，屬于所有崗位里最輕松的，不過想能搞明白電路各種參量的關(guān)系，也絕非易事。 畫模擬版圖的貌似跟電路設(shè)計(jì)正好相反，很多新招聘的版圖員甚至不知道啥是三極管，然后被培訓(xùn)幾天后就練習(xí)抄版圖，然后熟練了逐漸自己設(shè)計(jì)。這個(gè)職位基本只要明白各層次之間關(guān)系，不是色盲，手腳夠快，基本就能很快上手。不過這個(gè)職位也是所有職位里邊最辛苦的，要看著花花綠綠的顯示器不停的調(diào)整各個(gè)線條，而且版圖設(shè)計(jì)時(shí)間壓力一般也很大。一些私營公司的畫圖小妹甚至?xí)焕习辶R哭。這個(gè)職位可以說是最有屌絲氣息的一崗位，當(dāng)然如果熬出來收入也還不錯(cuò)，只是這個(gè)活計(jì)實(shí)在太費(fèi)眼。 現(xiàn)在大部分電路都是數(shù)模混合，全芯片整合用數(shù)字設(shè)計(jì)流程，所以很多模擬電路設(shè)計(jì)都是設(shè)計(jì)模塊，然后集成進(jìn)芯片，由于模擬部分尚且沒有標(biāo)準(zhǔn)的驗(yàn)證流程，也不能像數(shù)字電路那樣放進(jìn)fpga先跑跑看，而且模擬電路的測(cè)試設(shè)計(jì)也沒有明確規(guī)范，所以集成在一起的芯片大部分問題是由于模擬電路部分。相信隨著設(shè)計(jì)方法的改善與分工的細(xì)化，模擬電路方向會(huì)有更復(fù)雜的分工。 電路公司里邊其他職位，基本都是跟軟件或者整個(gè)系統(tǒng)相關(guān)了，這里就先介紹這些吧。對(duì)于其他的，如果有人比較了解，歡迎補(bǔ)充。之后我想整理一些對(duì)工作學(xué)習(xí)有幫助的網(wǎng)址，不知道是否有人有興趣 |
