作者:myshitshit 再來說說做數(shù)字后端版圖的大概情況 Job Description: · Interface with IC Design/Verification team (timing and power constraints definition) · Writing, running, optimization of logic and physical synthesis scripts · In-depth knowledge of STA. Ablility to handle timing analysis for multiple modes and corners · Physical design Floor planning, place & route, clock tree synthesis, routing cleanup · Power IR & EM analysis · Parasitic extraction/SPEF/SDF generation · Physical Verification (DRC, ERC, LVS, ANTENNA) · Deep understanding of DSM effects (sub 65 nm experience preferred) Requirements: · Masters/Bachelor’s Degree in Electrical/Electronics Engineering or in related field · Tool skills: · Synopsys Design Compiler · PERL, TCL languages · Prime Time and constraint creation/modification · IR analysis tool such as PrimeRail, Redhawk · Synopsys ICC experience preferred · Calibre · Ability to speak and write English is a must, CET 6 · Self-motivated team player and able to work with minimum supervision · Minimum 3 years of physical design and timing closure experience · Willingness to take overseas business trip 以上是一個(gè)數(shù)字版圖工程師的基本要求,現(xiàn)在大芯片后端綜合基本都用ICC,也有用SOC encounter的,版圖嚴(yán)重基本都是Calibre 這個(gè)工作除了要求熟練使用工具,掌握底層電路原理外,讀懂工藝文件,很需要一些耐心與細(xì)致的性格,因?yàn)橐话阕詣?dòng)生成的版圖未必能滿足所有時(shí)序要求,而且會(huì)有一些drc錯(cuò)誤,有時(shí)為了特殊目的也會(huì)做一些eco,這個(gè)就需要手工對版圖進(jìn)行一些編輯。面對滿眼的連線,要逐一修改切保證沒有失誤,是對體力與腦力的雙重考驗(yàn)。對這個(gè)工作崗位的要求其實(shí)也蠻高,不過由于其中一些雜活很耗費(fèi)體力,所以一般公司也會(huì)找新人幫忙做后端的打雜工,然后逐漸學(xué)習(xí)成長。由于此類工具license基本是整個(gè)ic設(shè)計(jì)環(huán)節(jié)中最貴的,所以能有機(jī)會(huì)做后端綜合的人不太多,當(dāng)然開的工資相對于邏輯設(shè)計(jì)也就屬于比較高的,這就相對于飛行員的工資比卡車司機(jī)高一樣。 當(dāng)然一般做后端設(shè)計(jì)的除了某些公司招聘的應(yīng)屆生逐漸上手的,還有一些是做手工版圖的后來轉(zhuǎn)行干這個(gè),因?yàn)檫@個(gè)職位相對于全手工畫圖,工作量還是小一些的,而且聽上去更高級(jí)一點(diǎn)。一旦開始做這個(gè)東西,基本就沒有什么其他相關(guān)職位可以轉(zhuǎn)行去干了,做資深工程師是唯一選擇。 再說說仿真驗(yàn)證工程師的要求 Job Description: Create verification plans for both block level and SoC level verification Create testbenches in SystemVerilog with OVM/UVM Utilize advanced verification techniques Write tools and scripts in Perl and other script languages to enhance the verification process Qualifications: Experience with SystemVerilog and OVM/UVM Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys) Experience with standard IP blocks and protocols such as Ethernet, TCP/IP, IPSec, iSCSI, DDR3, PCIe Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers Experience with tools for regression management, configuration management and bug tracking Good software skills in object oriented programming (OOP), C, C++, Perl, csh Good problem solving BS, MS or PhD in computer science or engineering 很久以前做數(shù)字電路的是沒有專門的驗(yàn)證工程師的,甚至現(xiàn)在小點(diǎn)的公司,這個(gè)任務(wù)也由做數(shù)字邏輯的兼任。不過現(xiàn)在大部分項(xiàng)目都是整合ip,驗(yàn)證的工作量反而更大一些,所以專門分離出來這個(gè)崗位,F(xiàn)在主流趨勢都是用SV的UVM,不過也有很多繼承之前項(xiàng)目的要用specman,當(dāng)然也有繼續(xù)用verilog寫驗(yàn)證平臺(tái)的,整體來說這個(gè)工作更適合之前習(xí)慣寫C++的人來做,對于習(xí)慣了RTL代碼的人,需要些時(shí)間接受這些以前專門用在軟件開發(fā)方面的思維方式。這個(gè)工作主要是設(shè)計(jì)驗(yàn)證平臺(tái),驗(yàn)證用列并協(xié)同邏輯設(shè)計(jì)人員查找錯(cuò)誤。很多公司新招的畢業(yè)生都會(huì)先做幾天驗(yàn)證測試,跑跑仿真,這說明這個(gè)工作是門檻比較低的,但是這個(gè)門檻低僅針對開發(fā)驗(yàn)證用列,設(shè)計(jì)一個(gè)高效方便的驗(yàn)證平臺(tái)并不是很簡單的事情,很多公司仍然沿用Verilog編寫的驗(yàn)證環(huán)境,估計(jì)主要因?yàn)檎也坏饺四艽罱ㄒ粋(gè)基于新方法學(xué)有效的驗(yàn)證環(huán)境。這個(gè)工作估計(jì)是電路設(shè)計(jì)崗位里邊最接近碼農(nóng)的,當(dāng)然也是需求人數(shù)最多的。這個(gè)崗位所開的工資,從畢業(yè)生的6,7k到大忽悠的20k以上,都是可能的,當(dāng)然這個(gè)工作做成了領(lǐng)導(dǎo),手下的人也是最多的。 |